Taiwan Semiconductor Manufacturing Company (TSMC) is facing a significant challenge to its decade-long dominance in advanced packaging as the physical scale of next-generation artificial intelligence (AI) accelerators pushes against the technical boundaries of its Chip on Wafer on Substrate (CoWoS) platform. During an earnings call on April 20, 2026, TSMC executives addressed reports that the increasing complexity and surface area of high-performance computing silicon are driving major customers to evaluate alternative packaging architectures.
The primary technical constraint involves the reticle limit, the maximum area a lithography machine can expose in a single step, which is approximately 858 square millimeters. According to a Morgan Stanley research report released on April 19, Google’s next-generation Tensor Processing Unit (TPU), codenamed “HumuFish,” features a silicon interposer that has reached nine times the reticle size, or nearly 80 square centimeters. This represents a threefold increase in size over the previous generation and approaches the current ceiling of TSMC’s CoWoS-L technology, which is targeted to reach 5.5 times the reticle size in 2026 and 9.5 times by 2027.
In response to these scaling pressures, Intel’s Embedded Multi-die Interconnect Bridge (EMIB-T) technology has emerged as a competitive alternative. Unlike CoWoS, which utilizes a large silicon interposer, EMIB-T employs small silicon bridges embedded directly into the package substrate to connect adjacent dies. This modular approach allows for significantly larger total package sizes, with Intel’s roadmap supporting up to 12 times the reticle size. Industry analysis indicates a substantial cost differential, with EMIB packaging estimated in the low hundreds of dollars per chip compared to approximately $900 to $1,000 for CoWoS on a Rubin-class accelerator. Intel also claims 90% wafer utilization for its bridge dies, significantly higher than the 60% utilization reported for large silicon interposers.
TSMC CEO C.C. Wei stated during the call that the company is actively advancing its own solutions to overcome these limitations, including a Chip-on-Panel-on-Substrate (CoPoS) pilot line expected to complete equipment installation by June 2026. Wei also highlighted the company’s System-on-Wafer (SoW) technology as a long-term option for customers requiring maximum integration. Despite these efforts, Intel CFO David Zinsner recently confirmed that Intel Foundry is close to securing packaging deals worth billions of dollars annually, with Google and Amazon identified as primary candidates for EMIB-T integration.
TSMC is continuing a massive capacity expansion to address the broader market, targeting 130,000 CoWoS wafer starts per month by late 2026, up from 60,000 in early 2025. However, the shift toward bridge-based architectures for the largest AI ASICs represents the first meaningful disruption to TSMC’s advanced packaging moat since the introduction of its Integrated Fan-Out technology.