On April 20, 2026, industry reports and technical specifications for Google’s next-generation Tensor Processing Unit (TPU) revealed that the chip’s physical scale is testing the architectural limits of Taiwan Semiconductor Manufacturing Company’s (TSMC) Chip on Wafer on Substrate (CoWoS) technology. For the first time since the inception of the CoWoS platform, major hyperscale clients are actively qualifying Intel Corporation’s Embedded Multi-die Interconnect Bridge (EMIB) as a primary alternative for high-performance AI silicon. This development follows a period of rapid scaling in AI model parameters that has necessitated larger silicon footprints than traditional packaging methods can easily accommodate.
The pivot comes as AI chip designs move toward system-on-wafer scales. TSMC’s current CoWoS-L and CoWoS-R configurations, while industry standards, face reticle limit constraints that complicate the integration of more than eight High Bandwidth Memory (HBM) stacks alongside massive logic dies. Google’s upcoming TPU, designed to handle trillion-parameter model training, requires a package size exceeding 3.5 times the standard reticle field. While TSMC has announced roadmaps for 5.5x reticle sizes by 2027, the immediate production requirements for 2026 have led Google to evaluate Intel’s EMIB, which offers a more modular approach to interconnecting multiple dies without the same monolithic interposer constraints.
Intel Foundry Services has positioned its EMIB and Foveros technologies as open-system foundry models. Intel CEO Pat Gelsinger previously confirmed that the company’s assembly and test facilities in Malaysia and Oregon are being outfitted to handle third-party silicon, specifically targeting high-volume clients like Google and Amazon Web Services. The EMIB technology uses small silicon bridges embedded in the package substrate rather than a large, expensive silicon interposer, which allows for larger total package footprints and improved thermal management for chips consuming over 1,000 watts.
In response to the shifting landscape, TSMC Senior Vice President of Operations, Kevin Zhang, noted during a technical symposium that the company is accelerating the deployment of its CoWoS-S with glass substrates to improve signal integrity and structural rigidity for oversized packages. However, the transition to glass is not expected to reach high-volume manufacturing until late 2026. TSMC currently maintains over 80 percent of the advanced packaging market share for AI accelerators, serving Nvidia and AMD, but the Google-Intel collaboration represents a breach in TSMC's one-stop-shop model where it provides both front-end wafer fabrication and back-end packaging.
The scale of the AI infrastructure market has made packaging a primary bottleneck in the semiconductor supply chain. TSMC recently expanded its CoWoS capacity to roughly 40,000 wafers per month to meet Nvidia’s Blackwell architecture demands. Despite this expansion, the physical size requirements of the next generation of super-chips are forcing a diversification of the supply chain. Google’s decision to dual-source or migrate packaging to Intel signifies a shift in the industry's reliance on a single ecosystem for the world's most powerful computing hardware.