Taiwan Semiconductor Manufacturing Company (TSMC) has officially outlined its advanced semiconductor roadmap, detailing plans to begin trial production of sub-1nm process technology, designated as the A10 node, by 2029. This strategic milestone follows the company’s projected commencement of mass production for its 1.4nm (A14) process in 2028. The announcement, made during a technical briefing on April 20, 2026, underscores the company’s commitment to maintaining its lead in the global foundry market through aggressive node transitions and the integration of next-generation lithography tools.
The transition to sub-1nm technology represents a significant shift in transistor architecture and manufacturing precision. According to TSMC’s Senior Vice President of Business Development, Kevin Zhang, the A10 node will likely utilize Complementary Field-Effect Transistor (CFET) architecture. This design stacks n-type and p-type transistors on top of each other, a departure from the current nanosheet structures used in the 2nm (N2) process. The CFET approach is expected to provide a 15% to 20% increase in chip density and a corresponding improvement in power efficiency, addressing the escalating demands of high-performance computing and artificial intelligence applications.
To support the A10 and A14 nodes, TSMC has confirmed plans to integrate High-Numerical Aperture (High-NA) Extreme Ultraviolet (EUV) lithography systems. These machines, manufactured by ASML, are essential for printing the intricate patterns required at sub-2nm dimensions. TSMC’s roadmap indicates that while the A14 node will utilize a mix of standard EUV and High-NA EUV, the A10 node will rely more heavily on the advanced optics of High-NA systems to achieve the necessary resolution without the need for excessive and costly multi-patterning steps.
Infrastructure development is already underway to accommodate these future nodes. TSMC is expanding its presence in the Hsinchu Science Park and the Southern Taiwan Science Park to house the specialized cleanrooms required for A14 and A10 production. The company has coordinated with the Ministry of Economic Affairs in Taiwan to ensure sufficient power and water supplies for these facilities, which are expected to consume significantly more energy than previous generations due to the increased complexity of EUV operations.
The 1.4nm A14 process remains on track for volume production in 2028, following the 2nm N2 node which is currently entering its final stages of preparation for 2025. TSMC’s roadmap serves as a benchmark for the industry, as competitors such as Intel and Samsung Electronics also pursue sub-2nm targets. Intel’s 14A process and Samsung’s 1.4nm plans are currently slated for similar timeframes, creating a highly competitive environment for the world’s leading fabless chip designers who require the most advanced silicon for their next-generation products.