Intel Corporation officially announced the release of its 14A Process Design Kit (PDK) 1.0 today, marking a pivotal advancement in its roadmap to reclaim semiconductor manufacturing leadership. The 14A process, representing the 1.4-nanometer node, is the first in the industry to be designed specifically for High-Numerical Aperture (High-NA) Extreme Ultraviolet (EUV) lithography. Intel CEO Pat Gelsinger confirmed during a press briefing that the company has successfully integrated the ASML Twinscan EXE:5000 High-NA systems at its research and development site in Oregon, allowing for the precise patterning required for the 14A node's increased transistor density.
The rollout of PDK 1.0 enables external foundry customers to begin the formal design process for future silicon. Intel reported that several of the world’s largest technology companies, including Nvidia, Apple, Google, and AMD, are currently evaluating the 14A node for their next-generation hardware. While formal volume-production contracts are still being negotiated, Intel Foundry Services (IFS) expects to sign definitive manufacturing agreements with these major players by the fall of 2026. Kevin O’Buckley, Senior Vice President and General Manager of Foundry Services, stated that the early availability of the PDK is intended to provide customers with the necessary lead time to optimize complex architectures for the new node.
Technically, the Intel 14A process is engineered to deliver a 15% improvement in performance-per-watt and a 20% increase in logic density compared to the Intel 18A node. It utilizes an evolved version of the RibbonFET gate-all-around (GAA) transistor architecture and the PowerVia backside power delivery system. According to technical specifications released by Intel, the 14A-E (Evolution) variant, scheduled for a later release, will further refine these metrics. The company has committed approximately $15 billion in capital investment toward the construction and tooling of its Silicon Heartland facilities in Ohio and its existing campus in Hillsboro, Oregon, to support the high-volume manufacturing of 14A.
To support the ecosystem, Intel also announced deepened technical collaborations with Electronic Design Automation (EDA) and Intellectual Property (IP) providers, including Synopsys, Cadence, and Siemens EDA. These partnerships ensure that the 14A PDK 1.0 is compatible with standard industry design tools, which is essential for attracting third-party foundry business. Intel’s internal product teams are also slated to use the 14A node for the development of future server and client architectures. This dual-use strategy is designed to demonstrate the node's viability for both high-performance data center chips and power-efficient mobile processors.