Google is in advanced negotiations with Marvell Technology to co-develop two new custom processors optimized for artificial intelligence inference, according to reports released on April 20, 2026. The partnership represents a strategic expansion of Google’s semiconductor ecosystem as the company moves to challenge Nvidia’s market leadership in AI hardware. The collaboration focuses on two specialized designs: a memory processing unit (MPU) and a new version of the Tensor Processing Unit (TPU) built specifically for inference tasks.
The MPU is designed to operate alongside Google’s existing TPU infrastructure to mitigate memory-intensive bottlenecks that currently limit the performance of large language models. By separating memory operations from core compute tasks, Google aims to reduce latency and improve the efficiency of real-time AI responses. The second chip, an inference-optimized TPU, is engineered to handle the serving of AI models to end-users. This pivot toward dedicated inference silicon comes as industry demand shifts from model training to the high-volume execution of AI software.
This negotiation follows a sequence of major infrastructure deals finalized by Google earlier in the month. On April 6, 2026, Google extended its partnership with Broadcom through 2031 to ensure a steady supply of next-generation TPUs. Furthermore, on April 9, Google and Intel announced a multi-year collaboration to integrate Intel’s Xeon 6 processors, built on the 18A manufacturing process, into Google Cloud’s AI infrastructure. These CPUs are intended to manage the orchestration and data processing required for heterogeneous AI systems.
Google’s current flagship hardware, the seventh-generation TPU known as Ironwood, is currently being deployed to support massive workloads. Internal data indicates that Google expects to ship 4.3 million TPU units throughout 2026, part of a broader plan to reach 50 million units by 2028. This infrastructure already supports significant external customers; AI developer Anthropic recently secured access to 3.5 gigawatts of TPU-based compute, while Meta Platforms signed a multibillion-dollar agreement to utilize Google’s custom silicon for its own AI services.
While Nvidia’s graphics processing units (GPUs) remain the industry standard for training advanced models, Google is positioning its custom application-specific integrated circuits (ASICs) as a high-efficiency alternative for inference. Amin Vahdat, Google’s Vice President of AI Infrastructure, stated that the company is focused on delivering performance-per-watt advantages to lower the total cost of ownership for AI services. The proposed chips co-developed with Marvell are expected to enter the design completion phase by 2027.