TSMC introduced the A13 process technology today at the 2026 North America Technology Symposium in Santa Clara, California. The A13 node is a direct optical shrink of the A14 process, which the company announced in 2025. According to technical specifications released during the event, A13 provides a 6% reduction in die area compared to A14 while maintaining full backward compatibility with A14 design rules. This compatibility is intended to allow customers to migrate existing designs to the newer nanosheet transistor technology with minimal redesign effort. TSMC expects A13 to enter high-volume production in 2029, approximately one year after the scheduled rollout of the A14 node.
Alongside A13, TSMC previewed the A12 process technology, which serves as a platform enhancement for the A14 generation. A12 is specifically optimized for artificial intelligence (AI) and high-performance computing (HPC) applications by incorporating Super Power Rail technology. This backside power delivery system moves the power distribution network to the rear of the wafer, reducing voltage drop and improving power integrity for high-current compute dies. Like A13, the A12 node is slated for production in 2029.
The symposium also highlighted advancements in the 2nm platform. TSMC introduced N2U, a third-year extension of its 2nm technology that utilizes design-technology co-optimization (DTCO). N2U is projected to deliver speed gains of 3% to 4% or a power reduction of 8% to 10% compared to the N2P process, along with a modest logic density improvement of 2% to 3%. Production for N2U is scheduled for 2028. For specialty applications, the company announced N16HV, the first high-voltage process to utilize FinFET transistors. Targeted at display drivers, N16HV offers a 41% increase in gate density and a 35% reduction in power consumption compared to the older N28HV node.
In the field of advanced packaging and silicon photonics, TSMC confirmed that its Compact Universal Photonic Engine (COUPE) will begin production in 2026. This co-packaged optics solution integrates optical engines directly into the chip package, achieving a twofold increase in power efficiency and a tenfold reduction in latency compared to traditional pluggable board-level designs. The company is also expanding its Chip on Wafer on Substrate (CoWoS) technology, currently producing 5.5-reticle size units with plans for 14-reticle versions by 2028 to support the integration of up to 10 compute dies and 20 high-bandwidth memory stacks.
TSMC Senior Vice President Kevin Zhang addressed the company's lithography strategy, confirming that TSMC does not currently plan to adopt ASML’s High-NA EUV lithography tools for its roadmap through 2029. Zhang stated that the company’s research and development teams have found methods to continue scaling using existing EUV equipment and multi-patterning techniques. The company also confirmed that the A16 process is now slated for production in 2027. This strategy positions TSMC to maintain its production cadence while managing capital expenditures, which the company expects to reach approximately $56 billion this year.